1. Technical Field
This invention relates in general to semiconductor-based electronics and, more specifically, to devices and methods in, for example, delay locked loops for generating quadrature and other off-phase clocks. Such devices and methods are particularly applicable to synchronous semiconductor devices, such as Synchronous Dynamic Random Access Memories (SDRAMS).
1. State of the Art
As shown in FIG. 1, a conventional Delay Locked Loop (DLL) 10 receives an input clock CLKIN at a 0.degree. phase and generates an output clock CLKOUT that is 180.degree. out of phase with the input clock CLKIN.
More specifically, n Delay Elements 12 of the DLL 10 receive the input clock CLKIN and output a series of increasingly delayed clocks D.sup.1, D.sup.2, D.sup.3, D.sup.4, D.sup.5, . . . , D.sup.n. To illustrate this further, it may be the case, for example, that the delayed clocks D.sup.1, D.sup.2, D.sup.3, D.sup.4, D.sup.5 are out of phase with the input clock CLKIN by 1.degree., 20.degree., 30.degree., 4.degree., and 5.degree., respectively.
In response to the count from a 1-to-n counter 14, an n-to-1 mux (i.e., multiplexer) 16 selects one of the delayed clocks D.sup.1, D.sup.2, D.sup.3, D.sup.4, D.sup.5, . . . D.sup.n and outputs it as the output clock CLKOUT. The counter 14 is controlled by a phase detector 18 that compares the input clock CLKIN to the output clock CLKOUT. If the output clock CLKOUT lags the input clock CLKIN by less than 180.degree., the phase detector 18 directs the counter 14 to count up until the output clock CLKOUT lags the input clock CLKIN by exactly 180.degree.. Conversely, if the output clock CLKOUT lags the input clock CLKIN by more than 180.degree., the phase detector 18 directs the counter 14 to count down until the output clock CLKOUT lags the input clock CLKIN by exactly 180.degree.. Of course, "exactly" is a relative term, since the fineness of control the phase detector 18 has over the output clock CLKOUT is limited by the selection of delayed clocks D.sup.1, D.sup.2, D.sup.3, D.sup.4, D.sup.5, . . . , D.sup.n available from the n Delay Elements 12.
The DLL 10 described above generally works well for generating the 180.degree. out of phase output clock CLKOUT. However, there is often a need to generate off-phase clocks at, for example, 90.degree. and 270.degree. at the same time a 180.degree. clock is generated. Such off-phase clocks are generally referred to as "quadrature" clocks.
Accordingly, as shown in FIG. 2, another conventional DLL 20 is available for generating multiple clocks, including quadrature clocks. The DLL 20 receives an input clock CLKIN at a 0.degree. phase and generates an output clock CLKOUT that is 180.degree. out of phase and a quadrature clock CLKOUT that is 90.degree. out of phase.
More specifically, x Delay Elements 22 of the DLL 20 receive the input clock CLKIN and output a series of increasingly delayed clocks D.sup.1, D.sup.2, D.sup.3, D.sup.4, D.sup.5, . . . , D.sup.x. In response to the count from a 1-to-x counter 24, an x-to-1 mux 26 selects one of the delayed clocks D.sup.1, D.sup.2, D.sup.3, D.sup.4, D.sup.5, . . . , D.sup.x and outputs it as the quadrature clock CLKOUT at 90.degree.. At the same time, x Delay Elements 28 receive the quadrature clock CLKOUT at 90.degree. and output a series of increasingly delayed clocks D.sup.x+1, D.sup.x+2, D.sup.x+3, D.sup.x+4, D.sup.x+5, . . . D.sup.2x. In response to the count from another 1-to-x counter 30, another x-to-1 mux 32 selects one of the delayed clocks D.sup.x+1, D.sup.x+2, D.sup.x+3, D.sup.x+4, D.sup.x+5, . . . , D.sup.2x and outputs it as the output clock CLKOUT at 180.degree..
The counters 24 and 30 are controlled by a phase detector 34 that compares the input clock CLKIN at 0.degree. to the output clock CLKOUT at 180.degree.. If the output clock CLKOUT lags the input clock CLKIN by less than 180.degree., the phase detector 34 directs the counters 24 and 30 to count up until the output clock CLKOUT lags the input clock CLKIN by exactly 180.degree.. Conversely, if the output clock CLKOUT lags the input clock CLKIN by more than 180.degree., the phase detector 34 directs the counters 24 and 30 to count down until the output clock CLKOUT lags the input clock CLKIN by exactly 180.degree.. As stated above, "exactly" is a relative term, since the fineness of control the phase detector 34 has over the output clock CLKOUT is limited by the selection of delayed clocks available from the n Delay Elements 22 and 28.
The DLL 20 described above thus provides multiple clocks, including quadrature clocks. However, the output clock CLKOUT generated by the DLL 20 has one-half the resolution of the output clock CLKOUT generated by the DLL 10 (FIG. 1). An example will illustrate this. Suppose that the change in phase between successive delayed clocks output by the Delay Elements 12 (FIG. 1), 22, and 28 is 1.degree.. As a result, the output clock CLKOUT generated by the DLL 10 (FIG. 1) is accurate to within 1.degree., while the output clock CLKOUT generated by the DLL 20 is only accurate to within 2.degree.. Such a reduction in resolution does not provide acceptable performance for today's high-speed electronics.
Therefore, there is a need in the art for devices and methods in, for example, delay locked loops for generating quadrature and other off-phase clocks with improved resolution.